Using multiple computers to simultaneously run multiple tasks, particularly where the tasks are related or need to interact, requires some communication facility between the multiple computers and tasks. For instance, if one processor needs the results from a calculation being made by another processor, the first processor can either wait until the other processor stores the result in a shared memory and then retrieve it, or the first processor can request the result directly from the other processor. These communications are usually accomplished via a "bus" or signal pathway between the multiple computers. However, having multiple computers communicating back and forth either between themselves or with the shared memory can create problems of contention for access to the bus pathway as multiple agents simultaneously vie for access to the same bus and/or to the same local resource.
One prior approach to resolving contention for bus access is to allow bus access on a time allocation basis, much like a task timesharing environment with a single computer running multiple tasks. While this approach avoids bus contention altogether, it makes no attempt at providing bus access on an as-needed basis and instead merely gives each processor bus access when it is that processor's time-slice, whether it needs it or not, and regardless of whether one processor's urgency or priority is any greater or lesser than any other processor's urgency or priority. Also, there is additional overhead incurred when switching from one processor accessing the bus to another processor accessing the bus.
Another prior approach to resolving bus access contention is to have a central arbitrator whose job it is to decide who gets access to the bus and when. While this does handle the "traffic cop" job, it requires separate circuitry just to handle the bus contention. Additionally, a central arbitrator usually increases the number of signal lines in the system. For instance, each processor which contends for bus access will likely require two signal lines; one for bus access requests to the central arbitrator and one for approval for bus access from the central arbitrator. Further, the central monitor will need to be able to monitor the bus itself in order to be able to intelligently manage the bus arbitration function. The central monitor will thus likely need some direct bus connection. Therefore, a central arbitration approach has the disadvantages of additional dedicated specialized circuitry, additional dedicated arbitration signal lines, and occupation of a slot on the bus in order to monitor the bus.